module test_psr ();

reg OVi, OVEN, CBi, CBEN, ZRi, CLK, nRESET, GEN;
wire OVo, CBo, ZRo;

initial
begin
	nRESET = 0; #10;
	OVi = 1;
	OVEN = 1;
	CBi = 1;
	CBEN = 1;
	ZRi = 1;
	CLK = 0;
	nRESET = 1;
	GEN = 1;
	#5; CLK = 1; #5; CLK = 0;
	OVi = 0;
	OVEN = 0;
	CBi = 0;
	CBEN = 0;
	ZRi = 0;
	#5; CLK = 1; #5; CLK = 0;
	OVi = 0;
	OVEN = 1;
	CBi = 0;
	CBEN = 1;
	ZRi = 1;
	#5; CLK = 1; #5; CLK = 0;
end

psr DUT (OVi, OVEN, CBi, CBEN, ZRi, CLK, nRESET, GEN, OVo, CBo, ZRo);

endmodule